Neuro-Inspired Temporal Logic

Neuro-Inspired Temporal Logic

Computing with Time

What happens if we try to do computation with values encoded only as times?

Computing with Time

When extremely low-energy processing is required, the choice of data representation makes a tremendous difference and we have much to learn from nature in this regard. For example the brain seems to use some form of “time-based” representations – encodings where the temporal relationship between spike arrivals carries useful information. This research asks the seemingly simple question: what happens if we try to do computation with values encoded only as times?

You can read a great summary of our race trees work by Adrian Colyer on the morning paper.

While we don’t know how to fully answer that question yet, our early results are encouraging and point to radically more energy efficient forms of computing. Under “race logic” information is represented as a timing delay, and a set of basic operations – MIN, MAX, ADD-CONSTANT, and INHIBIT – describe the basic set of “temporal operators” replacing the AND, OR, NOT we know and love from digital logic.

MAX

Given two input events arriving at time T1 and T2, output an event at time max(T1, T2).

MIN

Given two input events arriving at time T1 and T2, output an event at time min(T1, T2).

ADD-CONSTANT

Given one input event arriving at time T, output an event at time T+K for some constant K.

INHIBIT

Given a data input arriving at Td and a control input arriving at Tc, output an event at time Td if and only if Td < Tc.

The core idea of race logic is to deliberately engineer “race conditions” using these operators, where the time it takes to complete a task tells you the answer you are looking for. For example, we have constructed systems where the time it takes for a signal to reach the output tells you how closely related two sequences of DNA are to one another, or how to classify an image from a collection of digits.

Edges as a Proxy for Spikes

A race tree evaluated in time: rising edges on inputs x and y trigger inhibit, min, and max nodes, and the label whose edge arrives first at the output is the classification decision
The race tree toolchain: a scikit-learn model and hardware specs feed a compiler that maps trained trees to race logic hardware, with power and area models for design space exploration

A Practical Analog Implementation of Race Logic

Die micrograph of the analog race logic DNA alignment chip, with circuit and layout details of the race array and its unit cell
Micrograph of the Race Logic chip with its major functional units highlighted. The Race Logic array is an explicit implementation of the edit graph, and is reconfigured every computation based on the input patterns. (b) and (c) show a 10 × 10 race array with MIM-caps and local bias network. The local bias networks receive their control input from the global bias network. Panels (d) and (e) show the circuit and layout of the unit cell which is tiled to construct the whole array, while panels (f) and (g) show symmetric OR gate design and delay element.
George Tzimpragos and Tim Sherwood accepting the Best Paper Award at ASPLOS 2019 (presented by program co-chair Emmett Witchel)
George Tzimpragos and Tim Sherwood accepting the Best Paper Award at ASPLOS 2019 (presented by program co-chair Emmett Witchel)
The original race logic paper was one of 12 articles featured in IEEE Micro Top Picks for 2014
The original race logic paper was one of 12 articles featured in IEEE Micro Top Picks for 2014

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